1. Field of the Invention
The present invention relates to a semiconductor capacitor structure, and more particularly, to a semiconductor capacitor structure with high capacitor density for high voltage sustain, which can be applied to a semiconductor process below or 28 nm.
2. Description of the Prior Art
In semiconductor manufacturing processes, metal capacitors constituted by metal-insulator-metal (MIM) capacitor structures are widely applied in Ultra Large Scale Integration (ULSI) designs. Due to their lower resistance, less significant parasitic effect, and absence of induced voltage shift in the depletion region, metal capacitors with MIM capacitor structure are usually adopted as the main choice of semiconductor capacitor designs.
However, since the manufacturing cost for the MIM capacitor structure is very expensive, mainly due to the additional photomask(s) required in the manufacturing process, and as the cost becomes more significant along with development of advanced semiconductor manufacturing process technologies, an interdigitated metal capacitor of metal-oxide-metal (MOM) structure, which only engages in the standard CMOS manufacturing process, has been developed in accordance with a requirement for a more economical semiconductor manufacturing process technology.
In a prior art, a multilevel interdigitated semiconductor capacitor structure is defined, wherein the multilevel interdigitated semiconductor capacitor structure includes at least a plurality of odd layers, a plurality of even layers, and a plurality of dielectric layers. The plurality of odd layers and the plurality of even layers comprise a first electrode and a second electrode. The first electrode in the plurality of odd layers is coupled to the first electrode in the plurality of even layers through a first bus. Likewise, the second electrode in the plurality of odd layers is coupled to the second electrode in the plurality of even layers through a second bus.
Please refer to FIG. 1 and FIG. 2 together. FIG. 1 is a simplified diagram of an odd layer 10 of a conventional multilevel interdigitated semiconductor capacitor structure. FIG. 2 is a simplified diagram of an even layer 20 of the conventional multilevel interdigitated semiconductor capacitor structure. As shown in FIG. 1, the odd layer 10 comprises a first electrode 11 and a second electrode 15. The first electrode 11 includes a first section 12, and a plurality of second sections 13 arranged in parallel. The first section 12 includes a first portion 12A and a second portion 12B. The first portion 12A and the second portion 12B respectively constitute the two strokes of the L-shaped first section 12. The plurality of parallel-arranged second sections 13 join the first portion 12A of the first section 12, and are separated from one another by a predetermined distance. The second electrode 15 includes a first section 16, and a plurality of second sections 17 arranged in parallel. The first section 16 includes a first portion 16A and a second portion 16B. The first portion 16A and the second portion 16B respectively constitute the two strokes of the L-shaped first section 16. The plurality of parallel-arranged second sections 17 join the first portion 16A of the first section 16, and are separated from one another by a predetermined distance. The plurality of second sections 13 of the first electrode 11 and the plurality of second sections 17 of the second electrode 15 interdigitate with each other in parallel.
As shown in FIG. 2, the even layer 20 includes a first electrode 21 and a second electrode 25. The first electrode 21 includes a first section 22, and a plurality of second sections 23 arranged in parallel. The first section 22 includes a first portion 22A and a second portion 22B. The first portion 22A and the second portion 22B respectively constitute the two strokes of the L-shaped first section 22. The plurality of parallel-arranged second sections 23 join the first portion 22A of the first section 22, and are separated from one another by a predetermined distance. The second electrode 25 includes a first section 26, and a plurality of second sections 27 arranged in parallel. The first section 26 includes a first portion 26A and a second portion 26B. The first portion 26A and the second portion 26B respectively constitute the two strokes of the L-shaped first section 26. The plurality of parallel-arranged second sections 27 join the first portion 26A of the first section 26, and are separated from one another by a predetermined distance. The plurality of second sections 23 of the first electrode 21 and the plurality of second sections 27 of the second electrode 25 interdigitate with each other in parallel. The second section 13 of the first electrode 11 in FIG. 1 is perpendicular to the second section 23 of the first electrode 21 in FIG. 2.
However, in the conventional multilevel interdigitated semiconductor capacitor structure, since the dielectric parameter between the metal pitch (for example, the pitch between the second sections 13 of the first electrode 11 and the second sections 17 of the second electrode 15 in FIG. 1) is low (i.e. low k, such as 2.63), the metal pitch is required to be enlarged to achieve a better reliability (for example, the metal pitch is required to be 0.18 micrometers when the voltage is 6.6V), but it will cause huge capacitance decrease. In addition, due to the characteristics of the semiconductor process below 28 nm and the large voltage swing (such as 6V) in the PA design, an innovative semiconductor capacitor structure is required to fulfill the high voltage reliability issue (i.e. for high voltage sustain).